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ADVANCED GRID-CONNECTED MULTILEVEL INVERTER WITH REDUCED COMPONENTS AND ENHANCED POWER QUALITY FOR RENEWABLE ENERGY APPLICATIONS

Area: Electrical Engineering Department
Abstract: Grid-interfaced renewable-energy systems require power electronic converters that deliver high waveform quality with low semiconductor stress and low component count. The cross-connected multilevel inverter (CC-MLI) recently reported by Pathak et al. is an attractive reduced-device-count baseline: it produces nine single-phase output levels using only eight semiconductor switches, four capacitors and two DC sources, without a polarity-changing H-bridge, and it has been validated in MATLAB/Simulink for a standalone 24 V + 24 V laboratory-scale load. Three measurable limitations motivate this work: the nine-level resolution caps the low-order staircase total harmonic distortion (THD) of the output voltage at approximately 11.5 % at a modulation index of 0.85 (analytically derived in this paper); the capacitor self-balancing property is asserted but neither modelled nor proven; and no grid-connected control, filtering, synchronization or robustness study is presented. This paper develops a single, verifiable advancement over that baseline: an asymmetric-ratio cross-connected multilevel inverter (AsCC-13L) for grid-connected renewable-energy applications. By re-rating the right-hand module of the unchanged eight-switch skeleton to V2 = 2·V1, the identical hardware eight switches, four capacitors, two DC sources synthesises thirteen equidistant voltage levels of step V1/2, lowering the analytically-derived staircase THD floor to approximately 7.1 % at the same modulation index while preserving the total-standing-voltage-to-peak-output ratio of 4.5 and the count of three conducting devices per state. A charge-integral analysis proves that, under the proposed state assignment, the per-fundamental-cycle net charge drawn from each capacitive divider midpoint is identically zero for any power factor; hence the baseline's self-balancing property survives the asymmetrisation exactly. A complete grid-connected design is additionally developed: dwell-integral capacitor sizi
Author: Vinay Pathak¹, Kishor Thakre², Prateek Nigam³
DOI: MJAP/05/2058
Page: 119-145
Paper Id: 2058
Publication Date: 10-Sep-2026
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